The AutobusGW-30 is an FPGA-based high density Automotive Bus Ethernet Gateway capable of providing access for up to 30 Automotive Bus ports in a 1U compact and modular design.
Under the hood is a Xilinx Ultrascale+ Zynq SoC featuring an FPGA with Quad Core ARM Cortex-A53 processors. The tight integration of ARM processors and FPGA allows high port density without compromising performance.
The AutobusGW is a modular platform. Every group of 6 front-panel interfaces are internally controlled by a IO-Module Daughterboard implementing support for a particular Automotive Bus standard. Is it therefore possible to configure the AutobusGW according to the customer’s needs. The following is an example configuration:
The interface is a TCP based ASCII protocol which allows sending and receiving of automotive bus packets. It is also possible to schedule the transmission of frames which takes place periodically with high accuracy, while only changing the payload over TCP when required.
The AutobusGW is under active development and is expected to be available according to the following schedule: